1. Field of the Invention
The present invention relates to a memory system used for a computer system, and in particular, to a multichip package (Multi-Chip-Package; MCP) type memory system, and is applied to, for example, the field required for miniaturization of memories in a portable device.
2. Description of the Related Art
Generally, a memory integrated circuit (memory LSI) and an input/output (I/O) device which are connected to a computer system are accessed under the control of a central processor unit (CPU) of the system. However, if the CPU carries out transmitting and receiving data via a system bus while carrying out the entire management of the system bus, a load on the CPU is increased. Then, conventionally, a DMA (Direct Memory Access) mode is used, and data transfer between memory LSIs, or between a memory LSI and an input/output device is efficiently carried out, and the load on a CPU is reduced.
FIGS. 15 and 16 show a system configuration and operations when data transfer is carried out between two memory LSIs by using a DMA mode in a conventional computer system.
When DMA transfer is carried out, a system bus 90 is controlled by, not a CPU (not shown), but a DMA controller 91. On the basis of instructions (a chip select signal /CS, a read enable signal /RE, a write enable signal /WE, address data (Ao to Ai) on an address bus (Address Bus)) from the DMA controller 91, data is read on a data bus (Do to Dj) on the system bus 90 from a transfer origin memory in a memory system 100, the data is temporarily stored in a data buffer in the DMA controller 91, and thereafter, the data is written into a transfer destination memory in the memory system 100. In the meantime, because the CPU is free from a job of data transfer, and can carry out another job, the processing efficiency of the CPU as the entire system can be improved.
However, in execution of DMA transfer, because data read/write operations are carried out via the system bus 90, the system bus 90 is occupied by the data read/write operations during a period of time of the number of cycles corresponding to the number of items of data to be transferred, and the efficiency of the entire system is reduced.
As described above, the conventional computer system has the problem that the efficiency of the entire system is reduced because the system bus 90 is occupied by data read/write operations during a period of time of the number of cycles corresponding to the number of items of data to be transferred.
Note that, in a data processing apparatus in Jpn. Pat. Appln. KOKAI Publication No. 2001-243173, there is disclosed the point that a DMA controller controlling high-speed transfer between two RAMs is provided.
FIG. 17 shows a configuration example of another conventional computer system. Reference numeral 101 denotes a CPU, reference numeral 90 denotes a system bus formed from an address bus, a data bus, and a control signal bus, reference numeral 92 denotes a memory integrated circuit (LSI) such as, for example, a dynamic memory (Dynamic Random Access Memory; DRAM), and reference numeral 100A denotes a memory system.
The memory system 100A has, for example, a NOR type flash memory 93, a static type memory (Static Random Access Memory; SRAM) 94, and a NAND type flash memory 95. A system starting program including a control program needed at the time of system starting is usually stored in the NOR type flash memory 93, and the CPU 101 reads and executes the system starting program at the time of system starting.
The reason for that the system starting program is stored in the NOR type flash memory 93 is that, because a random access read rate in the NOR type flash memory 93 is about 60 ns to 70 ns which is relatively high, even if a program code is executed while being directly read out of the NOR type flash memory 93, the speed performance of the entire computer system is unaffected.
On the other hand, in the NAND type flash memory 95, as compared with the NOR type flash memory 93, a random access read rate is slower, and write/erase operations and serial read operation are faster. Moreover, because a memory cell area is small, an even lower-priced bit cost can be realized. An application of the NAND type flash memory 95 is suitable for recording a file such as an image or audio data which is frequently updated to some extent, and of which reading is serially carried out.
In consideration of such a characteristic of the flash memory, in recent years, in a system for a portable telephone, or the like, a NOR type flash memory is used for recording a program, and a NAND type flash memory is used for recording a file such as an image or audio data. In the future, it is anticipated that, when a bit capacity in an application for recording a file such as an image or audio data is increased for the entire system, a flash memory for recording a file will become dominant among nonvolatile memories in terms of capacity.
On the basis of the above background, a request that a memory packaging area is made smaller by using only a NAND type flash memory suitable for recording a file as a flash memory for use in a computer system, and moreover, the bit cost of the entire system is reduced has been made stronger from the system side.
On the other hand, a memory system used for a computer system such as a portable terminal or the like of which miniaturization of a device is strongly required has been required to be miniaturized, and in recent years, a multichip package (Multi Chip Package; MCP) type memory system in which a plurality of memory LSI chips are accommodated in a single package has started to be used. In such an MCP type memory system, it is expected that processing of a system starting program is appropriately carried out, and that an attempt is made to ensure adequate file recording capacity and reduction in bit cost.
As described above, the memory system used for the conventional computer system has the problem that, if a NOR type flash memory for storing a system starting program and another flash memory for recording a file are respectively used, a memory packaging area is increased, and the bit cost of the entire system rises.
Note that there is disclosed a technique of packaging a flash memory and a RAM into one package in Jpn. Pat. Appln. KOKAI Publication No. 5-299616. Further, in Jpn. Pat. Appln. KOKAI Publication No. 6-4410, there is disclosed a technique in which an EEPROM and a RAM having a capacity which is the same as that of the EEPROM are provided, data of the EEPROM is transferred to the RAM, usual reading and writing data are carried out with respect to the RAM, and the data is written into the EEPROM only when the data in the RAM is changed. Further, in Jpn. Pat. Appln. KOKAI Publication No. 11-353229, there is disclosed a technique in which a program stored in a flash memory is read out and written into a RAM at the time of system starting.